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MOTOROLA
SEMICONDUCTOR
APPLICATION NOTE
AN1241
Interfacing the MC68HC705J1A to
9356/9366 EEPROMs
By Mark Glenewinkel
CSIC Applications
INTRODUCTION
This application note describes the hardware and software interface used to communicate between the
Motorola MC68HC705J1A MCU and 9356/9366 EEPROM chips. The 93XX series of EEPROMs are an
industry standard used widely to store nonvolatile bits of information. The software listing in this application
note will work with 9356 and 9366 EEPROMs. The EEPROM bits are arranged in 128 or 256 16-bit
registers, respectively. With some modification, the software will work with other 93XX series EEPROMs.
Some of the applications in which EEPROMs can be utilized are listed below.
ID number for remote addressing or security
Storage of telecommunication information like phone number recall and speed dialing
Power down information storage for consumer electronics like TVs and VCRs
Reprogrammable calibration data for test/measurement equipment
The 93XX EEPROMs communicate with the outside world using a serial link. Since the MC68HC705J1A
does not have the hardware on chip to communicate to the EEPROM, a software driver is used. This
method bit programs an I/O port to properly transfer data to and from the EEPROM. A National
NM93C56N was used for testing the software routines in this application note.
HARDWARE INTERFACE
The 9356 is a very simple 8-pin device. Appendix A shows a typical connection between the
MC68HC705J1A and the 9356. The serial interface connection uses only four pins of the 9356. They are
as follows:
CS — Chip Select
SK — Serial Clock
DO — Serial Data Output
DI
— Serial Data Input
These signals must be clocked in a certain way in order to transfer the correct serial data to and from the
MC68HC705J1A.
©MOTOROLA, INC., 1995
AN1241/D
SOFTWARE INTERFACE
Communication between the MC68HC705J1A and the 9356 is done with a synchronous serial protocol. As
mentioned earlier, the MC68HC705J1A bit programs its I/O pins to communicate with the 9356. A timing
diagram of the serial link can be found in the 9356 data sheet if needed.
The 9356 will accept seven different commands. They are as follows:
1)
2)
3)
4)
5)
6)
7)
READ —
WRITE —
WRALL —
ERASE —
ERAL
WEN
WDS
Read a 16-bit data word from an address in memory
Write a 16-bit data word from an address in memory
Write all addresses with the same 16-bit data word
Erase a 16-bit data word from an address in memory
Erase all addresses within the memory map
Erase/write enable the EEPROM memory
Erase/write disable the EEPROM memory
The 9356 transmission format is a frame of data bits containing an opcode, an address, and if needed, a
word of data. The opcode is three bits long, the address is eight bits long, and the data word is 16 bits long.
Table 1 illustrates the bit information each instruction needs.
Table 1.
Instruction
READ
WEN
ERASE
ERAL
WRITE
WRALL
WDS
Opcode
110
100
111
100
101
100
100
Address
A7–A0
11XXXXXX
A7–A0
10XXXXXX
A7–A0
01XXXXXX
00XXXXXX
D15–D0
D15–D0
Data
IMPLEMENTATION AND TEST
Software was written to provide subroutines to perform each of the seven commands. A total of four bytes
of RAM are needed to support the subroutines. These bytes are described below.
1)
2)
3)
4)
OP_CODE — Contains the opcode needed for the command
ADDR
DATA_H
DATA_L
— Contains the address for the command
— The high byte for the data word
— The low byte for the data word
As needed, each EEPROM command subroutine will call other supporting subroutines to execute the
transmission of data between the MC68HC705J1A and the 9356. Appendix B contains flowcharts for all of
these subroutines.
MOTOROLA
2
AN1241/D
Each EEPROM command subroutine has input data and output data. This data is inherent with some
commands while others need the information passed to them before the subroutine is called. Table 2 lists
the input data needed and output data generated for each of the seven commands.
Table 2:
Command
READ
EWEN
ERASE
ERAL
WRITE
WRALL
EWDS
Subroutine Input
ADDR
ADDR
ADDR & DATA_H/L
DATA_H/L
Subroutine Output
DATA_H/L
Code was written and tested with a level of quality equal to the Carnegie-Mellon Software Engineering
Institute (SEI) Level 2. A test routine consisting of writing and reading the EEPROM is listed in Appendix C.
Refer to Appendix A for the schematic used in the design and test of the software. An LED is used to verify
that the test code works properly. The test routine executes the following:
1)
2)
3)
4)
5)
6)
7)
8)
Initializes the port on the HC705J1A for serial transmission. LED is turned off.
Writes EEPROM address $00 with $AA55.
Writes EEPROM address $20 with $1234.
Reads EEPROM address $00 and stores it to RAM location TEST1 and TEST2.
Reads EEPROM address $20 and stores it to RAM location TEST3 and TEST4.
Checks if TEST1 = $AA, TEST2 = $55, TEST3 = $12, and TEST4 = $34.
If check is good, then light the LED. If check is bad, do not light the LED.
Continue to run in an infinite loop until reset.
For increased reliability, the software watchdog on the MC68HC705J1A is used. Also, a low voltage inhibit
circuit, the MC34064, is used to decrease susceptibility to brown out or short power failure conditions.
SUMMARY
This application note has described the interface needed to successfully communicate between the
MC68HC705J1A and the 9356. For more information on the MC68HC705J1A, please consult the
Technical Data Manual, MC68HC705J1A/D. Contact National Semiconductor or SGS Thompson for
technical data on the 93XX series of EEPROM memories.
An electronic copy of the code listing in Appendix C and a listing of the test program to fully test all the
EEPROM commands can be found on the Motorola MCU BBS. The BBS number is (512) 891-3733. The
filename is j1a_9356.arc and is on the CSIC BBS under the APPNOTES directory.
Also, Motorola Application Note AN1221/D further details the software and hardware interfaces needed
between the 93XX series and other HC05 MCUs.
AN1241/D
MOTOROLA
3
APPENDIX A
MOTOROLA
4
AN1241/D
AN1241/D
HC705J1A to 93C56 Interface
VDD
VDD
2
1
9
10
GND
VDD
20
RESET
IRQ/VPP
19
CHIP_SELECT
SERIAL_CLOCK
SERIAL_OUT
SERIAL_IN
-->
-->
-->
<--
3
GND
U1
VDD
VSS
C1
0.1uF
1
2
3
4
U2
CS
VCC
SK
NC
DI
NC
DO
GND
NM93C56N
U3
INPUT
RESET
GND
MC34064
VDD
8
7
6
5
GND
VDD
X1
CER RES
3
1
2
GND
R1
390
D1
LED
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
1
2
18
17
16
15
14
13
12
11
8
7
6
5
4
3
PB0
PB1
PB2
OSC1
PB3
OSC2
PB4
PB5
MC68HC705J1AP
Motorola - CSIC Strategic Applications
Title
HC705J1A -> 93C56 EEPROM
Size Document Number
A
705J1A.SCH
Date:
February
9, 1995 Sheet
1 of
REV
1
1
MOTOROLA
5
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