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Motorola Semiconductor Application Note
AN1226
Use of the 68HC705C8A in Place of a 68HC705C8
By Russ Walin
CSIC Product Engineering
Austin, Texas
Introduction
This application note is intended to document the differences between
the 68HC705C8A and the 68HC705C8. It will also describe uses for the
"A" features (new features per customer requests), which include the
port B keypad interrupt/pull-ups, 68HC05C4A-type COP, and the high
current drive on port C. The pull-ups and C4A-type COP can be enabled
with two additional mask option registers (MOR).
Background
The 68HC705C8A is an enhanced version of the 705C8. It is designed
to be a drop-in replacement for the 705C8. There are some inherent
differences that the user should be aware of such as the port C7 current
drive characteristics, the MOR programming requirements, and the
geometries used in manufacturing. A bug with the SPI on the 705C8 was
fixed and the boot ROM code was changed.
© Motorola, Inc., 1996
AN1226 — Rev. 4
Application Note
Using the 705C8A in Place of a 705C8
Using the 705C8A in Place of a 705C8
When using the 705C8A in place of a 705C8, note the following points.
1. The most significant difference that exists when using the 705C8A
as a replacement for the 705C8 is the output current drive
capability on the port pin PC7 (port C bit 7) on the 705C8A. The
drive current was increased to provide LED drive capability on
PC7. The output drive characteristics of PC7 for both the 705C8
and the 705C8A are shown in
Figure 1.
There is no way to reduce
the PC7 drive current of the 705C8A to emulate the 705C8.
Characteristic
V
DD
= 5.0 V
±
10%
PC7 current drive (I
OH
)
@ V
OH
= V
DD
–0.8 V
PC7 current sink (I
OL
) @ V
OL
= 0.4 V
V
DD
= 3.3 V
±
10%
PC7 current drive (I
OH
)
@ V
OH
= V
DD
–0.3 V
PC7 current sink (I
OL
) @ V
OL
= 0.3 V
MC68HC705C8
MC68HC705C8A
0.8 mA
1.6 mA
5.0 mA
20.0 mA
0.2 mA
0.4 mA
1.5 mA
6.0 mA
2. Two additional MOR registers have been added on the 705C8A.
To emulate the 705C8, the MOR1 and MOR2 must not be
programmed (i.e., the port B interrupts/pull-ups and C4A COP will
not be enabled). The erased state of the 705C8's EPROM is "0",
so the default is "A" features disabled. That is, $00 must be
programmed into locations $1FF0–1FF1. On the 705C8 locations,
$1FF0–1FF1 are EPROM bytes that are reserved for test.
Depending on the programmer used, these bytes on the 705C8
may or may not be programmed. For example, the Bootloader
board, described in
MC68HC705C8 Technical Data
(MC68HC705C8/D), programs the EPROM bytes at
$1FF0–1FF1, so the master EPROM (2764) must contain $00 at
locations $1FF0–1FF1.
3. Programming characteristics should be similar to the 705C8. The
programming voltage V
PP
for the 705C8A should be V
PP
=
14.5–15.0 V, as with the 705C8. The programming times also
remain unchanged at 2 ms/byte.
AN1226 — Rev. 4
2
MOTOROLA
Application Note
Using the 705C8A in Place of a 705C8
705C8A Typical
705C8 Typical
.
.
705C8 Spec
705C8A Spec
0.5
5.0
0.4
4.8
V
OL
(VOLTS)
0.2
V
OH
(VOLTS)
0
10
I
OL
(mA)
20
30
0.3
4.6
4.4
0.1
4.2
0.0
4.0
0
5
I
OH
(mA)
10
MC68HC705C8A
+5 V
MC68HC705C8A
I
OH
PC7
V
OL
PC7
V
OH
I
OH
Figure 1. PC7 V
OL
/I
OL
and V
OH
/I
OH
Comparison of the 705C8
and the 705C8A V
DD
= 5.0 Volts
AN1226 — Rev. 4
MOTOROLA
3
Application Note
Using the 705C8A in Place of a 705C8
4. The 705C8A is made with 1.2 micron CMOS technology whereas
the 705C8 is made with 1.75 micron technology. The operating
I
DD
, wait I
DD
and stop I
DD
of the 705C8A are all similar to 705C8,
and the maximum I
DD
specifications remain unchanged.
5. A bug with the 705C8 SPI has been corrected on the 705C8A.
When the 705C8A SPI is in slave mode with CPHA = 1 and
CPOL = 0, the SPIF bit occasionally will not become set, wrongly
indicating an incomplete transmission. This problem was
corrected on the 705C8A. Because of this, the SPI slave mode
enable lag time is larger than that of the 705C8. The SPI slave
mode enable lag time is RATE * 1.5 (RATE = 1/frequency).
6. The code in the Boot ROM location $1F00–$1FEF has been
changed. The 705C8A contains Boot 7C8A Rev. 3.0 code.
7. The function of several bits in the PROG registers ($1C) have
changed. These bits were not implemented on the 705C8. On the
705C8A, bits 1 and 3–7 are implemented as test bits. The bits
should always be written as "0".
This change will affect programmer manufacturers and users who
use their own programming algorithm.
Bit 7
$1C
U
U
6
U
= Unused
5
U
4
U
3
U
2
LAT
1
U
Bit 0
PROG
Figure 2. 705C8 PROG Register
Bit 7
$1C
T
T
6
T
5
T
4
T
3
T
2
LAT
1
T
Bit 0
PROG
= Reserved for test. Always write"0".
Figure 3. 705C8A PROG Register
AN1226 — Rev. 4
4
MOTOROLA
Application Note
Using the Additional "A" Features of the 705C8A
Using the Additional "A" Features of the 705C8A
The 705C8A has several features added due to customer requests,
which are referred to as the "A" features. These features include the
C4A-type COP, the port B interrupts/pull-ups, and the LED drive
capability of PC7.
The C4A-type COP is similar to the 705C8 with the exception of the
timeout period, which is fixed at (1/f
OSC
) * 2
18
(see Figure 2). The C4A-
type COP is implemented with an 18-bit ripple counter. It has a timeout
period of 64 milliseconds at a bus rate of 2 MHz. This COP is intended
for use with the emulation of a 68HC05C4A. The C4A-type COP is
enabled by programming the EPROM bit 0 (NCOPE) at address $1FF1
to a "1". If COP times out, a system reset will occur. The COP is cleared
by writing a "0" to the PBPU0/COPC bit (bit 0) at location $1FF0.
Reading location $1FF0 will return the contents of MOR1. Location
$1FF0 is also the address used to enable the pull-up resistors; however,
writing a "0" to reset the COP will not have any effect on the state of the
pull-ups.
The 705C8-type COP is implemented as part of the 16-bit timer. To
enable the 705C8-type COP, the C4A COP should be disabled (EPROM
bit 0 at location $1FF1 should not be programmed). The 705C8-type
COP is enabled by setting the COPE bit (bit 2 at location $001E) to a "1".
The 705C8-type COP uses 11 bits of the 16-bit timer, which includes a
/4 fixed prescalar. This yields a 2
15
divide by (see
Figure 4).
There are
three other options for the timeout period that are determined by the
state of CM0/CM1 (bit 1 and bit 0 of the COP control register $1E). The
timeout period for various timeout periods is shown in
Table 1.
The COP is reset by writing a $55 to the COP reset register at $1D, and
then writing an $AA to the COP reset register. For more information on
the 705C8-type COP, see
3.1.3 Computer Operating Properly (COP)
Watchdog Timer Reset
in
MC68HC705C8 Technical Data
(MC68HC705C8/D).
The 705C8A also contains interrupts and pull-ups on port B intended for
implementing a keypad. The pull-up simplifies hardware needed for a
AN1226 — Rev. 4
MOTOROLA
5

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