Synthesizing Unit <czujnik2>. Related source file is E:/projekty-vhdl/krzepecki3/auto3/synthesis/./../compile/czujnik2.vhd. Found 1-bit register for signal <Sreg0<0>>. Found 1 1-bit 2-to-1 multiplexers. Summary: inferred 1 D-type flip-flop(s). inferred 1 Multiplexer(s). Unit <czujnik2> synthesized. Synthesizing Unit <wt>. Related source file is E:/projekty-vhdl/krzepecki3/auto3/synthesis/./../src/wt.vhd. Found 4x2-bit multiplier for signal <$n0002> created at line 47. Summary: inferred 1 Multiplier(s). Unit <wt> synthesized. Synthesizing Unit <czujnik1>. Related source file is E:/projekty-vhdl/krzepecki3/auto3/synthesis/./../compile/czujnik1.vhd. Found 1-bit register for signal <Sreg0<0>>. Found 1 1-bit 2-to-1 multiplexers. Summary: inferred 1 D-type flip-flop(s). inferred 1 Multiplexer(s). Unit <czujnik1> synthesized. Synthesizing Unit <licznik>. Related source file is E:/projekty-vhdl/krzepecki3/auto3/synthesis/./../compile/licznik.vhd. Found finite state machine <FSM_0> for signal <Sreg0>. ----------------------------------------------------------------------- | States | 9 | | Transitions | 25 | | Inputs | 2 | | Outputs | 4 | | Clock | CLK (rising_edge) | | Reset | rst (positive) | | Reset type | asynchronous | | Reset State | s1 | | Power Up State | s1 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s). Unit <licznik> synthesized. Synthesizing Unit <ster>. Related source file is E:/projekty-vhdl/krzepecki3/auto3/synthesis/./../compile/ster.vhd. Found finite state machine <FSM_1> for signal <Sreg0>. ----------------------------------------------------------------------- | States | 8 | | Transitions | 15 | | Inputs | 5 | | Outputs | 5 | | Clock | CLK (rising_edge) | | Reset | RST (positive) | | Reset type | asynchronous | | Reset State | s1 | | Power Up State | s1 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s). Unit <ster> synthesized. Synthesizing Unit <projekt>. Related source file is E:/projekty-vhdl/krzepecki3/auto3/synthesis/./../compile/projekt.vhd. Unit <projekt> synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... INFO:Xst:1784 - HDL ADVISOR - Multiplier(s) is(are) identified in your design. You can improve the performance of your multiplier by using the pipeline feature available with mult_style attribute. Advanced Registered AddSub inference ... FATAL_ERROR:Xst:Portability/expo rt/Port_Main.h:127:1.13 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com ERROR:NetListWriters:375 - Cannot open input file 'projekt.ngc' Synthesis finished with errors.
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