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CHAPTER 9
MSI LOGIC CIRCUITS
■
OUTLINE
9-1
Decoders
9-12
Data Busing
9-2
BCD-to-7-Segment
Decoder/Drivers
9-13
The 74ALS173/HC173
Tristate Register
9-3
Liquid-Crystal Displays
9-14
Data Bus Operation
9-4
Encoders
9-15
Decoders Using HDL
9-5
Troubleshooting
9-16
The HDL 7-Segment
Decoder/Driver
9-6
Multiplexers (Data
Selectors)
9-17
Encoders Using HDL
9-7
Multiplexer Applications
9-18
HDL Multiplexers and
Demultiplexers
9-8
Demultiplexers (Data
Distributors)
9-19
HDL Magnitude
Comparators
9-9
More Troubleshooting
9-20
HDL Code Converters
9-10
Magnitude Comparator
9-11
Code Converters
■
OBJECTIVES
Upon completion of this chapter, you will be able to:
■
Analyze and use decoders and encoders in various types of circuit
applications.
Compare the advantages and disadvantages of LEDs and LCDs.
■
Utilize the observation/analysis technique for troubleshooting digital
circuits.
■
Understand the operation of multiplexers and demultiplexers by
analyzing several circuit applications.
■
Compare two binary numbers by using the magnitude comparator
circuit.
■
Understand the function and operation of code converters.
■
Cite the precautions that must be considered when connecting digital
circuits using the data bus concept.
■
Use HDL to implement the equivalent of MSI logic circuits.
■
■
INTRODUCTION
Digital systems obtain binary-coded data and information that are continu-
ously being operated on in some manner. Some of the operations include:
(1)
decoding and encoding,
(2)
multiplexing,
(3)
demultiplexing,
(4)
compari-
son,
(5)
code conversion,
and (6)
data busing.
All of these operations and oth-
ers have been facilitated by the availability of numerous ICs in the MSI
(medium-scale-integration) category.
In this chapter, we will study many of the common types of MSI de-
vices. For each type, we will start with a brief discussion of its basic
operating principle and then introduce specific ICs. We then show how
they can be used alone or in combination with other ICs in various
applications.
9-1
DECODERS
A
decoder
is a logic circuit that accepts a set of inputs that represents a
binary number and activates only the output that corresponds to that in-
put number. In other words, a decoder circuit looks at its inputs, deter-
mines which binary number is present there, and activates the one output
that corresponds to that number; all other outputs remain inactive. The
577
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OGIC
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diagram for a general decoder is shown in Figure 9-1 with
N
inputs and
M
outputs. Because each of the
N
inputs can be 0 or 1, there are possible
input combinations or codes. For each of these input combinations, only
one of the
M
outputs will be active (HIGH); all the other outputs are LOW.
Many decoders are designed to produce active-LOW outputs, where only
the selected output is LOW while all others are HIGH. This situation is
indicated by the presence of small circles on the output lines in the decoder
diagram.
Some decoders do not utilize all of the possible input codes but only
certain ones. For example, a BCD-to-decimal decoder has a four-bit input
code and
ten
output lines that correspond to the
ten
BCD code groups 0000
through 1001. Decoders of this type are often designed so that if any of
the unused codes are applied to the input,
none
of the outputs will be
activated.
In Chapter 7, we saw how decoders are used in conjunction with counters
to detect the various states of the counter. In that application, the FFs in the
counter provided the binary code inputs for the decoder. The same basic de-
coder circuitry is used no matter where the inputs come from. Figure 9-2
shows the circuitry for a decoder with three inputs and outputs. It uses
all AND gates, and so the outputs are active-HIGH. Note that for a given in-
put code, the only output that is active (HIGH) is the one corresponding to
the decimal equivalent of the binary input code (e.g., output
2
N
2
N
2
3
=
8
O
6
goes HIGH
only when ).
This decoder can be referred to in several ways. It can be called a
3-line-
to-8-line decoder
because it has three input lines and eight output lines. It can
also be called a
binary-to-octal decoder
or
converter
because it takes a three-
bit binary input code and activates one of the eight (octal) outputs corre-
sponding to that code. It is also referred to as a
1-of-8 decoder
because only 1
of the 8 outputs is activated at one time.
CBA
=
110
2
=
6
10
FIGURE 9-1
General
decoder diagram.
A
0
A
1
A
2
O
0
O
1
O
2
N
inputs
M
outputs
Decoder
.
.
.
O
M–1
Only
A
N–1
2
N
input
codes
output
is HIGH for each
input code
one
ENABLE Inputs
Some decoders have one or more ENABLE inputs that are used to control the
operation of the decoder. For example, refer to the decoder in Figure 9-2 and
visualize having a common ENABLE line connected to a fourth input of each
gate. With this ENABLE line held HIGH, the decoder will function normally,
and the
A
,
B
,
C
input code will determine which output is HIGH. With
ENABLE held LOW, however,
all
of the outputs will be forced to the LOW
state regardless of the levels at the
A
,
B
,
C
inputs. Thus, the decoder is enabled
only if ENABLE is HIGH.
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9-1/
D
ECODERS
FIGURE 9-2
Three-line-to-
8-line (or 1-of-8) decoder.
0
O
0
= CBA
A
(LSB)
1
O
1
= CBA
2
O
2
= CBA
B
3
O
3
= CBA
4
O
4
= CBA
C
(MSB)
5
O
5
= CBA
6
O
6
= CBA
7
O
7
= CBA
C
B
A
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Figure 9-3(a) shows the logic diagram for the 74ALS138 decoder. By ex-
amining this diagram carefully, we can determine exactly how this decoder
functions. First, notice that it has NAND gate outputs, so its ou
tp
u
ts
ar
e
active-LOW. Another indication is the labeling of the outputs as
O
7
,
O
6
,
O
5
,
and so on; the overbar indicates active-LOW outputs.
The input code is applied at , and , where is the MSB. With
three inputs and eight outputs, this is a 3-to-8 decoder or, equivalently, a 1-of-8
decoder.
Inputs , and are separate enable inputs that are combined in the
AND gate. In order to enable the output NAND gates to respond to the input
co
de a
t
, this AND gate output mu
s
t be H
IG
H. This will occur only when
and . In other words, and are active-LOW, is active-
HIGH, and all three must be in their active states to activate the decoder out-
puts. If one or more of the enable inputs is in its inactive state, the AND output
will be LOW, which will force all NAND outputs to their inactive HIGH state
regardless of the input code. This operation is summarized in the truth table
in Figure 9-3(b). Recall that
x
represents the don’t-care condition.
The logic symbol for the 74ALS138 is shown in Figure 9-3(c). Note how
the active-LOW outputs are represented and how the enable inputs are rep-
resented. Even though the enable AND gate is shown as external to the
decoder block, it is part of the IC’s internal circuitry. The 74HC138 is the
high-speed CMOS version of this decoder.
A
2
,
A
1
A
0
A
2
E
1
,
E
2
E
3
A
2
A
1
A
0
E
1
=
E
2
=
0
E
3
=
1
E
1
E
2
E
3
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MSI L
OGIC
C
IRCUITS
FIGURE 9-3
(a) Logic
diagram for the 74ALS138
decoder; (b) truth table;
(c) logic symbol.
(MSB)
A
2
A
1
A
0
E
1
E
2
E
3
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
(a)
E
1
E
2
E
3
A
2
A
1
A
0
E
1
E
2
E
3
Outputs
E
0
1
X
X
0
X
1
X
1
X
X
0
Respond to input code A
2
A
1
A
0
Disabled – all HIGH
Disabled – all HIGH
Disabled – all HIGH
74ALS138
1-of-8 decoder
(b)
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
(c)
EXAMPLE 9-1
Indicate the states of the 74ALS138 outputs for each of the following sets of
inputs.
(a)
(b)
E
3
=
E
2
=
1,
E
1
=
0,
A
2
=
A
1
=
1,
A
0
=
0
E
3
=
1,
E
2
=
E
1
=
0,
A
2
=
0,
A
1
=
A
0
=
1
Solution
(a) With the decoder is disabled and all of its outputs will be in their
inactive HIGH state. This can be determined from the truth table or by
following the input levels through the circuit logic.
(b) All of the enable inputs are activated, so the decoding portion is
en
-
abled.
I
t will decode the input code
E
2
=
1,
011
2
=
3
10
to activate output
O
3
.
Thus,
O
3
will be LOW and all other outputs will be HIGH.
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